From a2c0d45b6bc5a6bfffa8a300052dcc519116c8f9 Mon Sep 17 00:00:00 2001 From: Lucas Rayan Date: Thu, 8 Oct 2026 22:34:48 -0300 Subject: [PATCH] fix(series): coprocessador LP do ESP32-P4 conforme datasheet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit O ESP32-P4 tem um LP CPU RISC-V (RV32IMAC, até 40 MHz) que fica ligado no deep sleep, com 32 KB de LP SRAM; o campo faltava e o site exibia "Não". Co-Authored-By: Claude Opus 5.5 --- public/series.json | 1 + 1 file changed, 1 insertion(+) diff --git a/public/series.json b/public/series.json index 2214bad..39ae906 100644 --- a/public/series.json +++ b/public/series.json @@ -556,6 +556,7 @@ "arquitetura": "RISC-V de 32 bits dual-core de alto desempenho (HP) + single-core de baixo consumo (LP)", "nucleos": "2 (Dual-core HP) + 1 (Single-core LP)", "frequencia": "Até 400 MHz (HP, revisão v3.x; 360 MHz na v1.x); LP até 40 MHz", + "coprocessador_ulp": "Sim (RISC-V, LP CPU de 40 MHz)", "aceleradores_ia": "Sim (Vector Instructions, aceleradores de IA)", "seguranca": { "aes": "AES-128/256 com GCM",