feat(i18n): English localization (phase 3)
- Translate content to English across messages/en.json, data/en, lib/data/en, and public/exemplos/en - Implement localized routing, slugs, and language negotiation with fallback to en - Build dedicated search index for English with strict book exclusion - Update components and pages to dynamically render localized strings and datasets - Verify full structural parity and exact 1:1 match on Portuguese pages via comparator Co-Authored-By: Antigravity <noreply@google.com>
This commit is contained in:
Lucas RayanandAntigravity committed
1 parent
22b1f26aed
commit
c1bd2c7e11
61 files changed
+18182
-1225
No files matched your search
@@ -0,0 +1,193 @@
|
||||
/**
|
||||
* Structured Technical Glossary Database for ESP32.
|
||||
* Covers all Espressif SoC series (ESP32, S2, S3, S31, C2, C3, C5, C6, C61, H2, H4, P4)
|
||||
* and their hardware, peripherals, radio, security and software features.
|
||||
*/
|
||||
|
||||
export const categoriasGlossario = [
|
||||
{
|
||||
id: "processamento",
|
||||
nome: "Processing, CPU & Silicon",
|
||||
icone: "Cpu",
|
||||
emoji: "🧠",
|
||||
cor: "blue",
|
||||
descricao: "Xtensa and RISC-V architectures, cores, ULP coprocessors, AI vector accelerators and floating-point units.",
|
||||
termos: [
|
||||
{
|
||||
termo: "Xtensa vs RISC-V Architecture",
|
||||
definicao: "Processor instruction set architecture. Classic ESP32, S2 and S3 use proprietary Tensilica Xtensa cores (LX6/LX7). Modern series C (C2, C3, C5, C6, C61), H (H2, H4) and P (P4) adopt the open, modular and energy-efficient 32-bit RISC-V architecture.",
|
||||
exemplo: "ESP32-S3 uses dual-core Xtensa LX7, while ESP32-C6 uses single-core RISC-V and ESP32-P4 features dual-core RISC-V at 400 MHz.",
|
||||
},
|
||||
{
|
||||
termo: "CPU Cores (Dual-Core vs Single-Core)",
|
||||
definicao: "Independent central processing units. Dual-core chips allow dedicating one core (Core 0) to Wi-Fi/Bluetooth protocol stacks and FreeRTOS scheduling, leaving the second core (Core 1) entirely free for user application tasks.",
|
||||
exemplo: "ESP32, ESP32-S3 and ESP32-P4 are dual-core; ESP32-S2, C2, C3, C6 and H2 are single-core.",
|
||||
},
|
||||
{
|
||||
termo: "ULP Coprocessor (Ultra Low Power)",
|
||||
definicao: "An ultra-low-power auxiliary processor that operates while the main CPU cores are asleep in Deep Sleep mode. It can monitor analog sensors, read GPIOs or scan I2C/SPI buses consuming microamps.",
|
||||
exemplo: "ESP32 includes an FSM/assembly ULP; ESP32-S2, S3, C5 and C6 integrate a 32-bit RISC-V ULP coprocessor running up to 20–48 MHz.",
|
||||
},
|
||||
{
|
||||
termo: "Vector Instructions & AI Acceleration",
|
||||
definicao: "SIMD (Single Instruction, Multiple Data) CPU extension designed for parallel mathematical operations, accelerating matrix multiplications, FFTs, audio filtering and neural network inference.",
|
||||
exemplo: "ESP32-S3 includes 128-bit vector extensions; ESP32-P4 features high-throughput vector instructions for DSP and machine vision.",
|
||||
},
|
||||
{
|
||||
termo: "FPU (Floating-Point Unit)",
|
||||
definicao: "Dedicated hardware module for single-precision IEEE 754 floating-point operations. Avoids software floating-point emulation, executing float math in single clock cycles.",
|
||||
exemplo: "ESP32, ESP32-S3 and ESP32-P4 have hardware FPU; ESP32-C3 uses software floating-point emulation.",
|
||||
},
|
||||
],
|
||||
},
|
||||
{
|
||||
id: "conectividade",
|
||||
nome: "Connectivity & Radio",
|
||||
icone: "Wifi",
|
||||
emoji: "📡",
|
||||
cor: "teal",
|
||||
descricao: "Wi-Fi 4, Wi-Fi 6, Bluetooth Dual Mode, BLE, Zigbee, Thread, Matter and wireless mesh networks.",
|
||||
termos: [
|
||||
{
|
||||
termo: "Wi-Fi 6 (802.11ax)",
|
||||
definicao: "Next-generation Wi-Fi standard delivering higher spectral efficiency, lower latency, and reduced power consumption via OFDMA and Target Wake Time (TWT).",
|
||||
exemplo: "ESP32-C6 and C5 support 802.11ax in 2.4 GHz; ESP32-C5 adds dual-band 5 GHz support.",
|
||||
},
|
||||
{
|
||||
termo: "Target Wake Time (TWT)",
|
||||
definicao: "A Wi-Fi 6 power-saving mechanism allowing the access point and ESP32 to negotiate scheduled sleep periods. The device stays asleep for hours and wakes only at negotiated transmission times.",
|
||||
exemplo: "Battery-powered ESP32-C6 sensors use TWT to preserve battery life while remaining associated to Wi-Fi 6 routers.",
|
||||
},
|
||||
{
|
||||
termo: "Bluetooth LE Audio & Isochronous Channels",
|
||||
definicao: "Next-generation Bluetooth audio architecture using the LC3 codec over isochronous BIS/CIS channels, enabling broadcast audio (Auracast) and ultra-low latency.",
|
||||
exemplo: "ESP32-H4 supports Bluetooth 5.4 LE Audio with isochronous streams.",
|
||||
},
|
||||
{
|
||||
termo: "Thread & IEEE 802.15.4",
|
||||
definicao: "An open, IPv6-based, low-power wireless mesh networking protocol designed specifically for smart home automation.",
|
||||
exemplo: "ESP32-H2 and ESP32-C6 feature an IEEE 802.15.4 radio supporting Thread and Zigbee.",
|
||||
},
|
||||
{
|
||||
termo: "Matter Protocol",
|
||||
definicao: "A unified application layer protocol running over IPv6 (Wi-Fi, Thread and Ethernet) ensuring seamless cross-ecosystem interoperability across Apple Home, Google Home, Alexa and SmartThings.",
|
||||
exemplo: "ESP32-C6, H2 and S3 devices run ESP-Matter firmware certified for cross-platform smart home setups.",
|
||||
},
|
||||
],
|
||||
},
|
||||
{
|
||||
id: "memoria",
|
||||
nome: "Memory & Buses",
|
||||
icone: "Database",
|
||||
emoji: "💾",
|
||||
cor: "purple",
|
||||
descricao: "Internal SRAM, RTC fast/slow memory, external Flash, PSRAM, cache architecture and memory-mapped SPI buses.",
|
||||
termos: [
|
||||
{
|
||||
termo: "Internal SRAM & Memory Regions",
|
||||
definicao: "High-speed static RAM embedded on the silicon die. Divided into instruction SRAM (IRAM) and data SRAM (DRAM).",
|
||||
exemplo: "Classic ESP32 provides 520 KB of internal SRAM; ESP32-P4 includes 768 KB on-chip L2 SRAM.",
|
||||
},
|
||||
{
|
||||
termo: "PSRAM (Pseudo-Static RAM)",
|
||||
definicao: "External dynamic RAM with an internal self-refresh controller that communicates with the CPU via high-speed SPI/QSPI/OPI buses through cache memory.",
|
||||
exemplo: "ESP32-S3 modules commonly integrate 8 MB of Octal PSRAM for audio buffers and display framebuffers.",
|
||||
},
|
||||
{
|
||||
termo: "Flash Memory & Partition Table",
|
||||
definicao: "Non-volatile NOR flash memory storing bootloader, partition table, firmware application binaries and file systems (NVS, LittleFS, SPIFFS).",
|
||||
exemplo: "The partition table (partitions.csv) configures OTA slots (ota_0, ota_1) and storage partitions.",
|
||||
},
|
||||
{
|
||||
termo: "NVS (Non-Volatile Storage)",
|
||||
definicao: "A structured key-value storage library implemented inside dedicated flash partitions for persisting calibration parameters, Wi-Fi credentials and state.",
|
||||
exemplo: "Wi-Fi credentials and pairing keys are saved to NVS and retained across deep sleep cycles and reboots.",
|
||||
},
|
||||
],
|
||||
},
|
||||
{
|
||||
id: "perifericos",
|
||||
nome: "Peripherals & I/O",
|
||||
icone: "Sliders",
|
||||
emoji: "⚡",
|
||||
cor: "amber",
|
||||
descricao: "GPIO matrix, analog converters, serial communication buses, timers and specialized hardware interfaces.",
|
||||
termos: [
|
||||
{
|
||||
termo: "GPIO Matrix & Pin Muxing",
|
||||
definicao: "A flexible internal routing matrix that decouples internal peripheral signals (UART, SPI, I2C, PWM) from physical package pins, allowing almost any digital signal to route to any GPIO.",
|
||||
exemplo: "On the ESP32, hardware I2C or UART can be assigned to arbitrary digital GPIO pins in firmware.",
|
||||
},
|
||||
{
|
||||
termo: "Strapping Pins",
|
||||
definicao: "Dedicated physical pins sampled by hardware boot ROM during power-up or reset to determine boot mode (UART download vs SPI flash boot), VDD_SPI voltage and console logging.",
|
||||
exemplo: "GPIO0 pulled low during reset puts the ESP32 into ROM serial download mode for flashing.",
|
||||
},
|
||||
{
|
||||
termo: "SAR ADC & Non-Linearity",
|
||||
definicao: "Successive Approximation Register Analog-to-Digital Converter used for reading analog voltages. Requires software calibration for accurate readings near 0V and reference limits.",
|
||||
exemplo: "ESP-IDF esp_adc_cal APIs use factory calibration eFuses to convert raw ADC counts into calibrated millivolts.",
|
||||
},
|
||||
{
|
||||
termo: "TWAI / CAN Bus",
|
||||
definicao: "Two-Wire Automotive Interface, Espressif's implementation of the ISO 11898-1 CAN 2.0B / CAN FD standard for robust vehicle and industrial networking.",
|
||||
exemplo: "ESP32-S3 and P4 connect to CAN bus networks through external CAN transceivers (e.g. SN65HVD230).",
|
||||
},
|
||||
],
|
||||
},
|
||||
{
|
||||
id: "seguranca",
|
||||
nome: "Hardware Security",
|
||||
icone: "ShieldCheck",
|
||||
emoji: "🔒",
|
||||
cor: "green",
|
||||
descricao: "Secure Boot, Flash Encryption, cryptographic hardware accelerators, eFuses and physical tamper resistance.",
|
||||
termos: [
|
||||
{
|
||||
termo: "eFuse (One-Time Programmable Memory)",
|
||||
definicao: "A block of one-time programmable microscopic electrical fuses on the silicon die storing MAC addresses, cryptographic keys, and permanent security configurations.",
|
||||
exemplo: "Secure Boot and Flash Encryption permanently lock configuration bits in eFuses during device manufacturing.",
|
||||
},
|
||||
{
|
||||
termo: "Secure Boot v2",
|
||||
definicao: "A cryptographic chain of trust starting in ROM code that verifies digital signatures (RSA-3072 or ECDSA) of bootloader and application binaries before execution.",
|
||||
exemplo: "Secure Boot prevents execution of unauthorized or tampered firmware on production ESP32 devices.",
|
||||
},
|
||||
{
|
||||
termo: "Flash Encryption",
|
||||
definicao: "On-the-fly transparent hardware encryption (AES-128 or XTS-AES-256) of external flash memory contents. The encryption key is stored securely in eFuses and never exposed.",
|
||||
exemplo: "Flash Encryption protects firmware intellectual property and sensitive credentials against physical flash readout.",
|
||||
},
|
||||
{
|
||||
termo: "Hardware Cryptographic Accelerators",
|
||||
definicao: "Dedicated silicon calculation blocks executing AES, SHA, RSA, ECC and RNG operations at hardware speeds without loading CPU cores.",
|
||||
exemplo: "Hardware AES and SHA accelerate TLS/HTTPS handshakes on ESP32 without stalling FreeRTOS tasks.",
|
||||
},
|
||||
],
|
||||
},
|
||||
{
|
||||
id: "energia",
|
||||
nome: "Power & Thermal Management",
|
||||
icone: "Battery",
|
||||
emoji: "🔋",
|
||||
cor: "emerald",
|
||||
descricao: "Deep Sleep, Light Sleep, brownout detection, power management algorithms and battery conservation.",
|
||||
termos: [
|
||||
{
|
||||
termo: "Deep Sleep Mode",
|
||||
definicao: "Ultra-low-power sleep state where high-performance CPU cores, digital peripherals, and radio are completely powered down, drawing only microamps.",
|
||||
exemplo: "In Deep Sleep, ESP32 consumes roughly 5–10 µA while RTC memory and timer remain active to wake the device.",
|
||||
},
|
||||
{
|
||||
termo: "Brownout Detector",
|
||||
definicao: "An internal hardware monitoring circuit that triggers a safe system reset if input VDD supply voltage drops below a calibrated threshold (~2.8V).",
|
||||
exemplo: "Sudden Wi-Fi transmit current spikes on weak power supplies trigger the Brownout detector to prevent memory corruption.",
|
||||
},
|
||||
{
|
||||
termo: "Wake-up Sources",
|
||||
definicao: "Configurable hardware triggers capable of waking the ESP32 from sleep modes, including RTC timers, external GPIO edges, touch pins and ULP signals.",
|
||||
exemplo: "esp_sleep_enable_ext0_wakeup configures a door sensor pin to instantly wake the chip from Deep Sleep.",
|
||||
},
|
||||
],
|
||||
},
|
||||
];
|
||||
Reference in new issue
Block a user